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Simucad's most current version, Silos-X, is sold as part of a tool-suite. Supports Verilog, VHDL and AHDL.Īs one of the low-cost interpreted Verilog simulators, Silos III enjoyed great popularity in the 1990s. Synopsys discontinued Purespeed in favor of its well-established VCS simulator.Īltera's simulator bundled with the Quartus II design software. FrontLine was sold to Avant!, which was later acquired by Synopsys. The simulator had a cycle-based counterpart called 'pure cycle'. ModelSim is still the leading simulator for FPGA design. Today Questa is the leading high performance SystemVerilog and Mixed simulator supporting a full suite of methodologies including industry standard OVM and UVM. In 2005 Mentor introduced Questa to provide high performance Verilog and SystemVerilog simulation and expand Verification capabilities to more advanced methodologies such as Assertion Based Verification and Functional Coverage. The original Modeltech (VHDL) simulator was the first mixed-language simulator capable of simulating VHDL and Verilog design entities together. ISE Simulator (ISim) provides support for mixed-mode language simulation including, but not limited to, simulation of designs targeted for Xilinx's FPGAs and CPLDs. Xilinx's simulator comes bundled with the ISE Design Suite. It also provides support for the e verification language, and a fast SystemC simulation kernel. The modern version of the NCsim family, called Incisive Enterprise Simulator, includes Verilog, VHDL, and SystemVerilog support. In response to competition from faster simulators, Cadence developed its own compiled-language simulator, NC-Verilog. It includes Designer, integrated Verilog and SystemVerilog debugging environment and has built-in support for multi-cpu simulation.Ĭadence initially acquired Gateway Design, thereby acquiring Verilog-XL. MPsim is a fast compiled simulator with full support for Verilog, SystemVerilog and SystemC. CVC has the ability to simulate in either interpreted or compiled mode. While ActiveHDL is a low-cost product, Aldec also offers a more expensive, higher-performance simulator called "Riviera."ĬVC is a Verilog HDL compiled simulator. Aldec licenses Active-HDL to FPGA-vendors, and the underlying engine can be found in the design-suites of those vendors. Commercial Simulators List of Verilog Simulators in Alphabetical Order by Name Simulator NameĪ simulator with complete design environment aimed at FPGA-applications.